Smart memories, or memories which appear externally as standard memory devices yet which contain on-chip processing capabilities, allow for implementation of massive parallel processing systems. As with all electronic circuits, however, the performance of such systems is dependent upon the reliability of each component within the system.
In parallel processing systems using smart memories, each of the smart memories forms an important component of the system that must operate reliably. Therefore, a need has arisen for a built-in self-test scheme for insuring the reliability of each smart memory. Furthermore, this built-in self-test scheme must operate quickly enough so as to not degrade the efficiency of the overall parallel processing system in which the smart memory resides.